With the increase in the grade and the number of functions of apparatus incorporating electronic components, the number of solder joints that connect electronic components to a printed circuit board has come to be very large. As a result, in designing an electronic apparatus, it is important to secure sufficient reliability of such solder joints.
There are electronic apparatus which are equipped with a storage device using semiconductor memories such as flash memories. In a BGA semiconductor package incorporating semiconductor memories, the semiconductor memories are mounted on a printed circuit board via solder bumps. The solder bumps are associated with various problems relating to the reliability of joining. And a particularly important problem is reduction in reliability due to the difference between the linear expansion coefficients of a BGA semiconductor memory package and a printed circuit board.
In an electronic apparatus, a temperature variation occurs repeatedly because of an operation of the apparatus and a variation in ambient temperature. During that course, solder bumps receive strong stress repeatedly due to the difference between the linear expansion coefficients of a BGA semiconductor memory package and a printed circuit board, resulting in fatigue cracks at a high probability. If the fatigue cracks advance to cause fatigue fracture, electrical continuity with the semiconductor memory concerned is lost there. The presence of this phenomenon lowers the reliability of the electronic apparatus to a large extent.
Where a storage device incorporates plural semiconductor memory packages, the level of thermal stress imposed is not uniform among the semiconductor memory packages. For example, it goes without saying that the level of thermal stress is higher and solder bumps suffer fatigue fracture sooner in semiconductor memories that are located in the vicinity of another component that heats to a high temperature (high heating component) or a support member of a printed circuit board than in the other semiconductor memories.
In connection with the reliability of semiconductor devices, a wear-leveling technique for performing rewriting on a large number of storage elements uniformly is well known as a technique for coping with the issue of the upper limit of the number of times of rewriting of each storage element. An example of such technique is disclosed in JP-A-2008-139927.
However, the technique disclosed in JP-A-2008-139927 is directed to detection of deterioration of memory cells and is hardly related to the reliability of solder mounting of a semiconductor memory package on a printed circuit board.
Thermal stress occurs repeatedly between a semiconductor memory package incorporating semiconductor memories and a printed circuit board due to the difference between their linear expansion coefficients. As a result, fatigue fracture may occur in solder bumps that connect them. In that event, trouble may occur in accessing the semiconductor memory concerned, that is, in writing or reading electronic data to or from it. In particular, there may occur trouble that valuable stored data is rendered unreadable.